1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit design and manufacturing, and more specifically to a 6T CMOS SRAM cell using tri-gate fully depleted substrate transistors and its methods of fabrication.
2. Discussion of Related Art
As silicon technology continues to scale from one generation to the next, the impact of intrinsic threshold voltage (Vt) variations in minimum geometry size bulk planar transistors reduces the CMOS SRAM cell static noise margin (SNM). This reduction in SNM caused by increasingly smaller transistor geometries is undesirable. SNM is further reduced when Vcc is scaled to a lower voltage.
Threshold voltage (Vt) variations in planar transistors arise mostly from the statistical fluctuation of the number and/or location of the dopant atoms in the depletion region of the transistors. The Vt variations pose barriers to the scaling of supply voltage, transistor size, and, hence, the minimum six transistor (6T) CMOS SRAM cell size. This limits the total transistor count for conventional 6T SRAM-dominated high performance CMOS ASICs and microprocessors due to die size and cost constraints.
Currently, the problem of reduced SNM resulting from Vt instability of the SRAM cell transistors is solved at the circuit/layout level by either (a) increasing the minimum supply voltage (Vccmin) needed to operate the cell and keeping the minimum geometry size transistors or (b) increasing the channel length and width of the cell transistors to enable a lower minimum operating voltage at the expense of the minimum cell size. At the device level, in planar devices, Vt mismatch arising from random dopant fluctuations (RDF) can be minimized by box-shaped wells or super-steep retrograde wells at the expense of additional fabrication process complexity.
A 6T CMOS SRAM cell circuit diagram using planar transistors is illustrated in FIG. 1. The SRAM cell consists of two N-type access devices 102, two N-type pull-down devices 104, and two P-type pull-up devices 106.
FIG. 2 illustrates a 6T CMOS SRAM cell layout using planar transistors. The gate of each access device is located in region 202. The gate of each pull-down device is located in region 204. The gate of each pull-up device is located in region 206. The gate regions are indicated by a region of polysilicon 214 over a region of P-type diffusion 212 or N-type diffusion 210. Metal layers 218 provide power (Vcc) and ground (Vss). Metal layers 218 may also connect the gate/source/drain of one planar transistor in the cell to the gate/source/drain of another transistor in the cell, and may interconnect one cell to another. Contacts 216 indicate regions where connections may be made to the metal layers. For a given Vcc, the cell ratio is tailored by sizing each access transistor width and each pull-down transistor width to achieve the maximum SNM value.
FIG. 3 is a graph 300 which illustrates the impact of supply voltage scaling on a typical 6T CMOS SRAM cell using planar transistors. The noise margin values assume nominal threshold voltage, nominal Vcc, and nominal device sizes. Dashed line 310 indicates the minimum desired value for SNM, 240 mV. The graph shows that as Vcc scales down from 2V to less than 1V, the cell ratio must increase in order to maintain a desirable SNM value. For a cell ratio of 1.5 (302), the minimum voltage that can be achieved while maintaining a nominal SNM of 240 mV is slightly less than 2.0V. When the cell ratio is increased to 2.0 (304), the minimum voltage that can be achieved while maintaining a nominal SNM is less than 1.5V. If the cell ratio is increased to 3.5 (306), the minimum voltage may be reduced to less than 1.0V. However, increasing the cell ratio corresponds to an area penalty in the form of increasing cell size.